Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Self test structure for interconnect and logic element testing in programmable devices

Self test structure for interconnect and logic element testing in programmable devices

US Patent 7779318 · Granted Aug 17, 2010

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Bio-based adhesive for electrical insulation2025
Communication logic to enhance area effectiveness for memory repair mechanism2025
System and method of geocoding2023
On-the-fly test and debug logic for ATPG failures of designs using on-chip clock2018
On-the-fly test and debug logic for ATPG failures of designs using on-chip clock2016
Re-headerer system and method2012
Framework for creating user interfaces containing interactive and dynamic 3-D ob2010
Method and process for producing a sequence of data request user interfaces2010
Efficient content addressable memory array for classless inter-domain routing2007
Systems for built-in-self-test for content addressable memories and methods of o2006