Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and system for low-power level-sensitive scan design latch with power-gated logic

Method and system for low-power level-sensitive scan design latch with power-gated logic

US Patent 7646210 · Granted Jan 12, 2010

Estimated economic value: $8,801,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fully automated chemiluminescence immunoassay analyzer2025
Display screen with graphical user interface2022
Systems and methods for generating templates for short-form media content2021
Testing integrated circuit designs containing multiple phase rotators2021
Testing integrated circuit designs containing multiple phase rotators2020
Testing integrated circuit designs containing multiple phase rotators2020
Testing integrated circuit designs containing multiple phase rotators2018
Validating manufacturing test rules pertaining to an electronic component2012
Indeterminate state logic insertion2012
Automatically creating manufacturing test rules pertaining to an electronic comp2011
Scanned memory testing of multi-port memory arrays2011
Multiplexor with leakage power regulator2010