Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency

Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency

US Patent 7617346 · Granted Nov 10, 2009

Estimated economic value: $4,744,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Initial signal generator, display panel and display method thereof, and display 2025
Computer system and network interface with hardware based packet filtering and c2016
Computer system and network interface supporting class of service queues2016
Method and apparatus for congestion and fault management with time-to-live2015
Method and apparatus for congestion and fault management with time-to-live2015
Method and apparatus for congestion and fault management with time-to-live2014
Method and apparatus for congestion and fault management with time-to-live2014
Method and apparatus for unified final buffer with pointer-based and page-based 2014
Method and apparatus for unified final buffer with pointer-based and page-based 2014
Method to support flexible data transport on serial protocols2014
Method to support flexible data transport on serial protocols2014
Method and apparatus to optimize class of service under multiple VCs with mixed 2013