Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same

Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same

US Patent 7542340 · Granted Jun 2, 2009

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Direct-bonded native interconnects and active base die2025
3D memory circuit2025
Transistor level interconnection methodologies utilizing 3D interconnects2025
Non-volatile dynamic random access memory2024
Multi-modal wide-angle illumination employing a compound beam combiner2024
Direct-bonded native interconnects and active base die2023
Transistor level interconnection methodologies utilizing 3D interconnects2023
3D memory circuit2023
Multi-die module with low power operation2022
Direct-bonded native interconnects and active base die2022
Back biasing of FD-SOI circuit blocks2021
Transistor level interconnection methodologies utilizing 3D interconnects2021