Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for improved single event latch up resistance in an integrated circuit

Method for improved single event latch up resistance in an integrated circuit

US Patent 7474011 · Granted Jan 6, 2009

Estimated economic value: $9,638,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Syndrome decoder circuit2025
Monotonic counter memory system2024
Memory device and multi physical cells error correction method thereof2022
Non-volatile memory device2021
Memory apparatus and data accessing method thereof2021
Memory storage apparatus with dynamic data repair mechanism and method of dynami2021
Encoding method and memory storage apparatus using the same2021
Error correction code memory device and codeword accessing method thereof2021
Memory apparatus having hierarchical error correction code layer2020
RRAM with plurality of 1TnR structures2020
Memory device having parameter adjusting mechanism and method of adjusting param2020
Encoding method and memory storage apparatus using the same2019