Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Automatic bit fail mapping for embedded memories with clock multipliers

Automatic bit fail mapping for embedded memories with clock multipliers

US Patent 7444564 · Granted Oct 28, 2008

Estimated economic value: $6,235,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Device, system and method for memory repair with multi-cell switching2025
Structures and methods for deriving stable physical unclonable functions from se2024
Voltage power switch2023
Voltage power switch2022
Charge trap memory devices2022
Selection circuit2020
Program and erase memory structures2020
Latching current sensing amplifier for memory array2020
Robust and error free physical unclonable function using twin-cell charge trap t2019
Margin test for multiple-time programmable memory (MTPM) with split wordlines2019
Circuit and method for detecting time dependent dielectric breakdown (TDDB) shor2018
Parallel programming of one time programmable memory array for reduced test time2018