Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of associating timing violations with critical structures in an integrated circuit design

Method of associating timing violations with critical structures in an integrated circuit design

US Patent 7380228 · Granted May 27, 2008

Estimated economic value: $6,448,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Automated timing optimization2012
Synthesized logic replacement2012
Control signal source replication2011
Statistical design closure2011
Optimizing test code generation for verification environment2010
Enhanced method of optimizing multiplex structures and multiplex control structu2009
On-the-fly RTL instructor for advanced DFT and design closure2008
Method and computer program for incremental placement and routing with nested sh2008
Method and computer program for incremental placement and routing with nested sh2008
Method and computer program for management of synchronous and asynchronous clock2008
Method of optimizing RTL code for multiplex structures2006
Automated analysis of RTL code containing ASIC vendor rules2006