Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Pipelined stop, start, address byte, and data byte technique and circuit for I2C logic system

Pipelined stop, start, address byte, and data byte technique and circuit for I2C logic system

US Patent 7366809 · Granted Apr 29, 2008

Estimated economic value: $18,663,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Protocol auto-detection2024
Apparatus and method of over-current limit for multi-channel digital-to-analog c2024
Hart-enabled device with reduced communication lines and break extension protoco2023
HART FSK digital demodulator2021
Haptics effect controller architecture and instruction set2014
Low power, high speed multi-channel data acquisition system and method2013
Method and system for providing security to processors2011
Pipelined clock stretching circuitry and method for I2C logic system2010
Pipelined clock stretching circuitry and method for I2C logic system2010
AFSM circuit and method for low jitter PLL CMOS programmable divider2010
Method and device for providing high data rate for a serial peripheral interface2008
Method and device for providing high data rate for a serial peripheral interface2008