Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methodology for designing high speed receivers below a target bit-error-rate

Methodology for designing high speed receivers below a target bit-error-rate

US Patent 7277828 · Granted Oct 2, 2007

Estimated economic value: $14,221,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Aminoacyl-tRNA synthetase efficiently introducing lysine derivatives2025
Current sensing by using aging sense transistor2025
Charge pumping using adjustable capacitor2025
Hydrogen and oxygen supplemental firing for combined-cycle facility2025
Method and circuit for DLL locking mechanism for wide range harmonic detection a2025
Data transmission method, terminal device, and computer-readable storage medium2025
Methods and apparatus to retime data using a programmable delay2025
Rotatable ring stand phone case2025
Clock recovery training2025
Phone case2025
Faucet extender for toddlers2025
Power transistor circuit that generates internal voltage supply2025