{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores", "item": "https://www.patentleaderboard.com/patent/7249331"}]}

Home › Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores

Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores

US Patent 7249331 · Granted Jul 24, 2007

Estimated economic value: $9,916,000 ⓘ

Assignee

IBM

Inventors

Pradip Bose (157 patents)
Tejas Karkhanis (14 patents)
Srinivasan Ramani (47 patents)
Malcolm S. Ware (109 patents)
Ken V. Vu (36 patents)

View full patent text on Google Patents →