Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of implementing off-chip cache memory in dual-use SRAM memory for network processors

Method of implementing off-chip cache memory in dual-use SRAM memory for network processors

US Patent 7200713 · Granted Apr 3, 2007

Estimated economic value: $17,128,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Boot initialization without home node involvement2025
Cache locality when using repurposed cache memory2025
Virtual wire protocol for transmitting side band channels2025
Node identification allocation in a multi-tile system with multiple derivatives2024
Coherent multiprocessing enabled compute in storage and memory2024
Load reduced nonvolatile memory interface2023
Peripheral component interconnect attributes shared using address bits2023
Load reduced nonvolatile memory interface2022
Payload cache2022
Caching for heterogeneous processors2021
Caching for heterogeneous processors2021
Caching for heterogeneous processors2021