Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for reducing electrical interconnection fatigue

Method and apparatus for reducing electrical interconnection fatigue

US Patent 7173342 · Granted Feb 6, 2007

Estimated economic value: $13,917,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electronic package with passive component between substrates2025
Stripped redistrubution-layer fabrication for package-top embedded multi-die int2025
Co-planar interconnection mechanisms for circuit boards2025
Through-substrate underfill formation for an integrated circuit assembly2025
Integrating system in package (SiP) with input/output (IO) board for platform mi2024
Multi-use package architecture2024
Stripped redistrubution-layer fabrication for package-top embedded multi-die int2024
Systems and apparatuses for implementing a pad on solder mask (POSM) semiconduct2023
Organic mold interconnects in shielded interconnects frames for integrated-circu2023
Wrappable EMI shields2023
Reverse-bridge multi-die interconnect for integrated-circuit packages2023
Stripped redistrubution-layer fabrication for package-top embedded multi-die int2023