Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Drain extended MOS transistors with multiple capacitors and methods of fabrication

Drain extended MOS transistors with multiple capacitors and methods of fabrication

US Patent 7166903 · Granted Jan 23, 2007

Estimated economic value: $16,757,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Reduced area single poly EEPROM2015
Method and circuit for curvature correction in bandgap references with asymmetri2014
Area-efficient electrically erasable programmable memory cell2013
Digital-to-analog converter with a shared resistor string2013
Area-efficient electrically erasable programmable memory cell2012
Single poly EEPROM without separate control gate nor erase regions2011
Area-efficient electrically erasable programmable memory cell2011
Analog single-poly EEPROM incorporating two tunneling regions for programming th2010
Circuits and methods to minimize nonlinearity errors in interpolating circuits2010
Method to detect poly residues in LOCOS process2010
Apparatus and method for compensating change in a temperature associated with a 2010
Circuit for generating a temperature dependent current with high accuracy2010