Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programmable logic device including multipliers and configurations thereof to reduce resource utilization

Programmable logic device including multipliers and configurations thereof to reduce resource utilization

US Patent 7142010 · Granted Nov 28, 2006

Estimated economic value: $6,167,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hazard mitigation for lightweight processor cores2025
Systems for and methods for mode hop detection in heat assisted magnetic recordi2025
FPGA specialist processing block for machine learning2025
Vector processor architectures2025
Rank-based dot product circuitry2025
High precision decomposable DSP entity2024
Systems for and methods for fast mode hop detection and correction for hard disk2024
Systems and methods for low latency modular multiplication2024
Programmable integrated circuit underlay2024
Efficient dual-path floating-point arithmetic operators2024
Integrated circuits with machine learning extensions2024
Floating-point dynamic range expansion2024