Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices

Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices

US Patent 6969649 · Granted Nov 29, 2005

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatus, semiconductor device, and redistribution layer structure thereof2025
Vehicle driving support system and vehicle driving support method2025
Bond pads for semiconductor die assemblies and associated methods and systems2025
Semiconductor device and substrate2025
Semiconductor wiring device and method2025
Semiconductor device and method of forming the same2025
Semiconductor device and manufacturing method thereof2025
Method for manufacturing semiconductor device2024
Semiconductor device and method of forming the same2024
Semiconductor device and method of forming the same2024
Apparatuses and methods of controlling hydrogen supply in memory device2024
Apparatuses and methods including patterns in scribe regions of semiconductor de2023