Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › DRAM cell arrangement with vertical MOS transistors, and method for its fabrication

DRAM cell arrangement with vertical MOS transistors, and method for its fabrication

US Patent 6939763 · Granted Sep 6, 2005

Estimated economic value: $82,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Field effect transistor having a dielectric structure2025
Integrated on-chip duplexer for simultaneous wireless transmission2016
Non-volatile memory cell with lateral pinning2013
Dual stage sensing for non-volatile memory2013
Apparatus for variable resistive memory punchthrough access method2013
Memory cell with stress-induced anisotropy2013
Tuning a variable resistance of a resistive sense element2012
Non-volatile memory cell with precessional switching2012
Non-volatile memory cell with non-ohmic selection layer2012
Magnetic stack design2012
Apparatus for variable resistive memory punchthrough access method2012
Variable resistive memory punchthrough access method2012