Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for rapid estimation of wire delays and capacitances based on placement of cells

Method for rapid estimation of wire delays and capacitances based on placement of cells

US Patent 6931610 · Granted Aug 16, 2005

Estimated economic value: $4,508,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Clustering for processing of circuit design data2015
Reduction of cross-talk noise in VLSI circuits2006
Timing optimization in presence of interconnect delays2003
System and method for estimating capacitance of wires based on congestion inform2003
System and method for estimating capacitance of wires based on congestion inform2003
Automated design of parallel drive standard cells2002
Generalized theory of logical effort for look-up table based delay models using 2001