Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory device having different burst order addressing for read and write operations

Memory device having different burst order addressing for read and write operations

US Patent 6931483 · Granted Aug 16, 2005

Estimated economic value: $1,281,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Configurable inputs and outputs for memory stacking system and method2013
Memory devices having programmable elements with accurate operating parameters s2012
System and method for mode register control of data bus operating mode and imped2007
System and method for mode register control of data bus operating mode and imped2007
Multi-mode synchronous memory device and methods of operating and testing same2006
Memory device having posted write per command2005
Multi-mode synchronous memory device and methods of operating and testing same2005
Multi-mode synchronous memory device and method of operating and testing same2004
Memory device having posted write per command2003
Integrated capacitor on the back of a chip2002
Vertical passive components for surface mount assembly2000