Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Mechanism to avoid explicit prologs in software pipelined do-while loops

Mechanism to avoid explicit prologs in software pipelined do-while loops

US Patent 6912709 · Granted Jun 28, 2005

Estimated economic value: $36,074,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Mobile device based techniques for detection and prevention of hearing loss2023
Web services comparison tool2021
Selecting a low power state based on cache flush latency determination2021
Mobile device based techniques for detection and prevention of hearing loss2020
Web services comparison tool2019
Selecting a low power state based on cache flush latency determination2019
Selecting a low power state based on cache flush latency determination2017
Web services comparison tool2016
Energy optimization techniques in a computing system2014
Generating communication protocol test cases based on network traffic2013
Method and system for performing reassociation in software loops2010
Method for predicate promotion in a software loop2010