Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography

Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography

US Patent 6898781 · Granted May 24, 2005

Estimated economic value: $30,688,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Diagnostic laboratory systems and methods of imaging tube assemblies2025
Apparatus and methods of identifying tube assembly type2025
Determining contour edges for an image2025
System and method for detecting anomalies in images2025
Methods and apparatus for protecting patient information during characterization2025
Hydrocarbon flow avatar2025
Methods and apparatus for hashing and retrieval of training images used in HILN 2025
Insights system2025
Parallel mask rule checking on evolving mask shapes in optical proximity correct2025
Method and systems for predicting a stream of virtual topograms2025
Change management service2024
Automatic sensor trace validation using machine learning2024