Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers

Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers

US Patent 6898674 · Granted May 24, 2005

Estimated economic value: $30,688,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Native support for execution of get exponent, get mantisssa, and scale instructi2025
Immediate offset of load store and atomic instructions2025
Sharing register file usage between fused processing resources2025
Systolic array having support for output sparsity2025
Register file for systolic array2025
High performance constant cache and constant access mechanisms2025
Virtualization and multi-tenancy support in graphics processors2025
Pointer de-referencing technologies2025
Systolic array of arbitrary physical and logical depth2024
Tanh and sigmoid function execution2024
Native support for execution of get exponent, get mantisssa, and scale instructi2024
Scalable sparse matrix multiply acceleration using systolic arrays with feedback2024