Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programmable logic devices with stabilized configuration cells for reduced soft error rates

Programmable logic devices with stabilized configuration cells for reduced soft error rates

US Patent 6876572 · Granted Apr 5, 2005

Estimated economic value: $75,693,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Passgate structures for use in low-voltage applications2010
Clock data recovery circuitry associated with programmable logic device circuitr2010
Dynamic RAM storage techniques2009
Passgate structures for use in low-voltage applications2009
Integrated circuit structures for increasing resistance to single event upset2008
Clock data recovery circuitry associated with programmable logic device circuitr2008
Integrated circuit structures for increasing resistance to single event upset2008
Apparatus for configuring programmable logic devices and associated methods2007
Dynamic RAM storage techniques2007
Clock data recovery circuitry associated with programmable logic device circuitr2007
Passage structures for use in low-voltage applications2006
Dynamic RAM storage techniques2006