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Home › Method and device for characterizing a CMOS logic cell to be produced in a technology of the partially depleted silicon-on-insulator type

Method and device for characterizing a CMOS logic cell to be produced in a technology of the partially depleted silicon-on-insulator type

US Patent 6871330 · Granted Mar 22, 2005

Estimated economic value: $10,073,000 ⓘ

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