Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Efficient ESD protection with application for low capacitance I/O pads

Efficient ESD protection with application for low capacitance I/O pads

US Patent 6858902 · Granted Feb 22, 2005

Estimated economic value: $26,573,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for efficient electrostatic discharge testing and analysis2020
ESD protection using diode-isolated gate-grounded nMOS with diode string2016
ESD protection using diode-isolated gate-grounded NMOS with diode string2014
ESD protection system optimized at board level2014
MOS device with substrate potential elevation for ESD protection2013
In package ESD protections of IC using a thin film polymer2011
Methodology to guard ESD protection circuits against precharge effects2011
MOS device with substrate potential elevation2010
Methodology to guard ESD protection circuits against precharge effects2010
Local ESD protection for low-capicitance applications2010
Circuit to reduce internal ESD stress on device having multiple power supply dom2009
Semiconductor dual guardring arrangement2008