Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Fail-safe zero delay buffer with automatic internal reference

Fail-safe zero delay buffer with automatic internal reference

US Patent 6768362 · Granted Jul 27, 2004

Estimated economic value: $3,475,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

ESD protection circuit2024
Programmable chopping architecture to reduce offset in an analog front end2023
ESD protection circuit2022
Analog to digital converter with floating digital channel configuration2022
Programmable chopping architecture to reduce offset in an analog front end2022
Method for fast detection and automatic gain adjustment in ADC based signal2022
Method for fast detection and automatic gain adjustment in ADC based signal2020
Digital-to-analog converter with a sample and hold circuit and a continuous-time2017
Dual protocol input device2014
Microcontroller with programmable logic2009
Current source architecture for memory device standby current reduction2007
ESD trigger circuit with injected current compensation2007