Assignee
Inventors
- Ivan E. Sutherland (67 patents)
- Josephus C. Ebergen (28 patents)
{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Determining transistor widths using the theory of logical effort", "item": "https://www.patentleaderboard.com/patent/6629301"}]}
Skip to contentUS Patent 6629301 · Granted Sep 30, 2003