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Home › Dual threshold voltage complementary pass-transistor logic implementation of a low-power, partitioned multiplier

Dual threshold voltage complementary pass-transistor logic implementation of a low-power, partitioned multiplier

US Patent 6615229 · Granted Sep 2, 2003

Estimated economic value: $46,907,000 ⓘ

Assignee

Intel

Inventors

Narsing Vijayrao (35 patents)
Chi Keung Lee (19 patents)
Kumar Sudarshan (2 patents)

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