Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Clock receiver circuit for on-die salphasic clocking

Clock receiver circuit for on-die salphasic clocking

US Patent 6614279 · Granted Sep 2, 2003

Estimated economic value: $46,907,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-buffered register files with shared access circuits2025
LSTM circuit with selective input computation2025
Multi-height interconnect trenches for resistance and capacitance optimization2025
Multi-height interconnect trenches for resistance and capacitance optimization2025
Apparatus and method for approximate trilinear interpolation for scene reconstru2025
Apparatus and method for approximate trilinear interpolation for scene reconstru2025
Instructions and logic to perform floating point and integer operations for mach2025
Instructions and logic to perform floating point and integer operations for mach2024
Instructions and logic to perform floating point and integer operations for mach2024
High bandwidth core to network-on-chip interface2024
Compute near memory with backend memory2023
LSTM circuit with selective input computation2023