Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for transistor-level calculation of the precharge time of domino logic circuits with unlocked evaluation paths

Method for transistor-level calculation of the precharge time of domino logic circuits with unlocked evaluation paths

US Patent 6601220 · Granted Jul 29, 2003

Estimated economic value: $10,466,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Remote verification for configuration updates2017
Signal transmission reducing coupling caused delay variation2016
Multiple-patterned semiconductor device channels2016
Remote verification for configuration updates2015
Multiple-patterned semiconductor device channels2015
Semiconductor device channels2015
Signal path and method of manufacturing a multiple-patterned semiconductor devic2015
Semiconductor device channels2015
Semiconductor device with distinct multiple-patterned conductive tracks on a sam2015
Signal path and method of manufacturing a multiple-patterned semiconductor devic2015
Method of making semiconductor device with distinct multiple-patterned conductiv2015
Signal path of a multiple-patterned semiconductor device2015