{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Gate electrode formation in double-recessed transistor by two-step etching", "item": "https://www.patentleaderboard.com/patent/6573129"}]}
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Home › Gate electrode formation in double-recessed transistor by two-step etching

Gate electrode formation in double-recessed transistor by two-step etching

US Patent 6573129 · Granted Jun 3, 2003

Estimated economic value: $17,799,000 ⓘ

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