Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Loop cache memory and cache controller for pipelined microprocessors

Loop cache memory and cache controller for pipelined microprocessors

US Patent 6567895 · Granted May 20, 2003

Estimated economic value: $20,266,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Microprocessor with an instruction immediately next to a branch instruction for 2005
Microprocessor with instructions for shifting data responsive to a signed count 2004
Self-priming loop execution for loop prolog instruction2001
Microprocessor2001
Interruptable multiple execution unit processing during operations utilizing mul2001
Method and apparatus for performing a shift instruction with saturate by examina2000
Microprocessor with an instruction for multiply and left shift with saturate2000
Optimized deterministic bearings only target motion analysis technique1998