Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening

Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening

US Patent 6566219 · Granted May 20, 2003

Estimated economic value: $97,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Infrared debond damage mitigation by copper fill pattern2025
Multiple chip bridge connector2021
Porous silicon relaxation medium for dislocation free CMOS devices2020
Third type of metal gate stack for CMOS devices2020
FinFET vertical flash memory2020
FinFET with epitaxial source and drain regions and dielectric isolated channel r2020
Fully depleted SOI device for reducing parasitic back gate capacitance2020
Multiple-bit electrical fuses2020
Hybrid aspect ratio trapping2020
Porous silicon relaxation medium for dislocation free CMOS devices2020
Integrated strained stacked nanosheet FET2019
Integrated circuit chip with molding compound handler substrate and method2019