Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method op optimizing vias between conductive layers in an integrated circuit structure

Method op optimizing vias between conductive layers in an integrated circuit structure

US Patent 6413872 · Granted Jul 2, 2002

Estimated economic value: $6,932,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fabrication technique using sputter etch and vacuum transfer2008
Fabrication of copper-containing region such as electrical interconnect2005
Method for manufacturing a compact bipolar transistor structure2003
Structure and method for controlling copper diffusion and for utilizing low K ma2002
Compact bipolar transistor structure2002
Process for formation of vertically isolated bipolar transistor device2001
Method for decreasing contact resistance of an electrode positioned inside a mis2001
Method for formation of an air gap in an integrated circuit architecture2001
Structure and method for controlling copper diffusion and for utilizing low K ma2000
Self-aligned copper interconnect structure and method of manufacturing same2000
Self-aligned interconnect using high selectivity metal pillars and a via exclusi2000
Method for forming self-aligned vias in multi-metal integrated circuits1999