Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of erasing a flash EEPROM memory cell array optimized for low power consumption

Method of erasing a flash EEPROM memory cell array optimized for low power consumption

US Patent 6282124 · Granted Aug 28, 2001

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Split gate FerroFET2025
Ferroelectric device2025
Method of producing hybrid semiconductor wafer2025
Memory structures and methods of processing the same2025
High force low voltage piezoelectric micromirror actuator2025
Micromirror arrays2025
Micromirror arrays2025
Memory device with ferroelectric charge trapping layer2024
Ferroelectric device based on hafnium zirconate and method of fabricating the sa2024
Hyperspectral image sensor with calibration2023
Three-dimensional ferroelectric memory2022
Method of forming a semiconductor device structure2022