Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programmable logic array devices with interconnect lines of various lengths

Programmable logic array devices with interconnect lines of various lengths

US Patent 6278291 · Granted Aug 21, 2001

Estimated economic value: $74,881,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Phase-locked loop architecture and clock distribution system2017
Phase-locked loop architecture and clock distribution system2016
PLD architecture for flexible placement of IP function blocks2015
PLD architecture for flexible placement of IP function blocks2015
Phase-locked loop architecture and clock distribution system2014
PLD architecture for flexible placement of IP function blocks2014
PLD architecture for flexible placement of IP function blocks2014
Apparatus for improving performance of field programmable gate arrays and associ2014
Phase-locked loop architecture and clock distribution system2013
Apparatus for configuring performance of field programmable gate arrays and asso2013
PLD architecture for flexible placement of IP function blocks2013
PLD architecture for flexible placement of IP function blocks2013