Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Superscalar instruction decoder including an instruction queue

Superscalar instruction decoder including an instruction queue

US Patent 6189087 · Granted Feb 13, 2001

Estimated economic value: $5,609,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Microprocessor with non-cacheable memory load prediction2024
Artificial selection method and reagents2019
General purpose register file architecture for aligned simd2006
Pipelined processor including a loosely coupled side pipe2005
Modulo address generation method and apparatus2003
Universal dependency vector/queue entry2003
Processor including efficient fetch mechanism for L0 and L1 caches2003
Processor configured to predecode relative control transfer instructions and rep2002
System having a configurable cache/SRAM memory2002
Resistive component for use with short duration, high-magnitude currents2002
Physical rename register for efficiently storing floating point, integer, condit2002
Instruction alignment unit for routing variable byte-length instructions2002