Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution

Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution

US Patent 6130552 · Granted Oct 10, 2000

Estimated economic value: $122,078,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Preform assembly for drawing multicore or holey optical fibre and method of manu2025
Cutoff shifted optical fibre2023
Cut-off shifted optical fibre with large effective area2022
Memory device random option inversion2021
Dynamic scan chain and method2021
Phase-locked loop architecture and clock distribution system2017
Phase-locked loop architecture and clock distribution system2016
FPGA configuration bitstream protection using multiple keys2015
FPGA configuration bitstream protection using multiple keys2015
PLD architecture for flexible placement of IP function blocks2015
PLD architecture for flexible placement of IP function blocks2015
FPGA configuration bitstream encryption using modified key2015