Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels

Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels

US Patent 6112267 · Granted Aug 29, 2000

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems, apparatuses, and methods for resource bandwidth enforcement2025
Method, apparatus and system for hierarchical network on chip routing2021
Cache allocation with code and data prioritization2018
Cross-die interface snoop or global observation message ordering2017
Technique for performing memory access operations via texture hardware2017
Technique for performing memory access operations via texture hardware2017
Load/store operations in texture hardware2017
Cache allocation with code and data prioritization2017
Surface resource view hash for coherent cache operations in texture processing h2016
Technique for accessing content-addressable memory2016
Relaxed coherency between different caches2015
Block linear memory ordering of texture data techniques2013