Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache

Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache

US Patent 6070233 · Granted May 30, 2000

Estimated economic value: $40,529,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Recording relevant information in a GUI window of a panel dump browser tool2010
Automatic analysis of memory operations using panel dump file2008
Displaying abnormal and error conditions in system state analysis2007
Control system for recreating of data output clock frequency which matches data 2001
Apparatus and method for compressing a plurality of contiguous addresses to form2000
Linear function generator method with counter for implementation of control sign2000
Processor bus traffic optimization system for multi-level cache utilizing reflec1999
Methods for accessing coincident cache with a bit-sliced architecture1999
Exponential functional relationship generator method and system for implementati1999
Digital device control method and system via linear function generator implement1999
Fast write initialization method and system for loading channel adapter microcod1999
Processor path emulation system providing fast readout and verification of main 1998