Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions

Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions

US Patent 6060387 · Granted May 9, 2000

Estimated economic value: $46,627,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor devices with enhanced electromigration performance2016
Method of manufacturing an enhanced electromigration performance hetero-junction2014
Method of forming electrical interconnects having electromigration-inhibiting se2006
Method of forming electrical interconnects having electromigration-inhibiting pl2005
Method of forming electrical interconnects having electromigration-inhibiting pl2004
Electrical interconnect structure having electromigration-inhibiting segments2001
Method of forming trench isolated regions with sidewall doping1994
Planarization process for trench isolation in integrated circuit manufacture1992
Precision resistor in self-aligned silicided MOS process1992
Method for providing a metal-semiconductor contact1992
Planarization process utilizing three resist layers1991