{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method of planarizing integrated circuits with fully recessed isolation dielectric", "item": "https://www.patentleaderboard.com/patent/6008107"}]}

Home › Method of planarizing integrated circuits with fully recessed isolation dielectric

Method of planarizing integrated circuits with fully recessed isolation dielectric

US Patent 6008107 · Granted Dec 28, 1999

Estimated economic value: $23,728,000 ⓘ

Assignee

National Semiconductor

Inventors

John M. Pierce (20 patents)
Sung Tae Ahn (28 patents)

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