Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions

Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions

US Patent 5996066 · Granted Nov 30, 1999

Estimated economic value: $84,965,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Graphical image data reformatting method and apparatus2002
Microprocessor with parallel inverse square root logic for performing graphics f2002
Computer system and method for fetching a next instruction2001
Central processing unit with integrated graphics functions2001
Instruction result labeling in a counterflow pipeline processor2001
Temporary pipeline register file for a superpipelined superscalar processor2000
Processor having a plurality of pipelines and a mechanism for maintaining cohere1999
Central processing unit with integrated graphics functions1999
Graphic system for masking multiple non-contiguous bytes having decode logic to 1999
Central processing unit with integrated graphics functions1999
Microprocessor having a cache memory system using multi-level cache set predicti1999
Multiple instruction dispatch system for pipelined microprocessor without branch1998