{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method of making EEPROM having coplanar on-insulator FET and control gate", "item": "https://www.patentleaderboard.com/patent/5960265"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of making EEPROM having coplanar on-insulator FET and control gate

Method of making EEPROM having coplanar on-insulator FET and control gate

US Patent 5960265 · Granted Sep 28, 1999

Estimated economic value: $25,907,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fractal analog random access memory2025
Counter based resistive processing unit for programmable and reconfigurable arti2025
Darlington pair bipolar junction transistor sensor2024
Low resistance contacts including intermetallic alloy of nickel, platinum, titan2024
Field effect transistor with controllable resistance2024
Direct growth of lateral III-V bipolar transistor on silicon substrate2024
Series connected stacked vertical transistors for high voltage applications2024
Counter based resistive processing unit for programmable and reconfigurable arti2024
Low resistance contacts including intermetallic alloy of nickel, platinum, titan2024
Field effect transistor with controllable resistance2023
Circuit methodology for highly linear and symmetric resistive processing unit2023
Selective application of multiple pulse durations to crossbar arrays2023