Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Catalytic acceleration and electrical bias control of CMP processing

Catalytic acceleration and electrical bias control of CMP processing

US Patent 5948697 · Granted Sep 7, 1999

Estimated economic value: $32,804,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Bond and probe pad distribution2016
Heat pipe in overmolded flip chip package2015
Integrated circuit package architecture2014
Integrated circuit package architecture2012
Reticle for wafer test structure areas2011
Reticle for layout modification of wafer test structure areas2008
Method and apparatus for monitoring yield of integrated circuits2007
Method and apparatus for operating a burn-in board to achieve lower equilibrium 2006
Techniques for reticle layout to modify wafer test structure area2005
Underfill for maximum flip chip package reliability2005
Catalytic acceleration and electrical bias control of CMP processing2000
Method of producing stepped wall interconnects and gates1999