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Home › Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an asynchronous partial reset and an asynchronous master reset

Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an asynchronous partial reset and an asynchronous master reset

US Patent 5860125 · Granted Jan 12, 1999

Estimated economic value: $4,051,000 ⓘ

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