{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method and structure for generating a boosted word line voltage and back bias voltage for a memory array", "item": "https://www.patentleaderboard.com/patent/5805509"}]}
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Home › Method and structure for generating a boosted word line voltage and back bias voltage for a memory array

Method and structure for generating a boosted word line voltage and back bias voltage for a memory array

US Patent 5805509 · Granted Sep 8, 1998

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