Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Bond pad option for integrated circuits

Bond pad option for integrated circuits

US Patent 5763298 · Granted Jun 9, 1998

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for testing fuse blow reliability for integrated circuits2017
DRAM security erase2017
DRAM security erase2016
Non-volatile memory devices having vertical drain to gate capacitive coupling2016
Power boosting circuit for semiconductor packaging2015
DRAM security erase2015
Embedded passive integration2015
Common doped region with separate gate control for a logic compatible non-volati2014
System and method for testing fuse blow reliability for integrated circuits2014
DRAM security erase2014
Power boosting circuit for semiconductor packaging2014
Data inversion register technique for integrated circuit memory testing2014