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Home › Method for forming minimum area structures for sub-micron CMOS ESD protection in integrated circuit structures without extra implant and mask steps, and articles formed thereby

Method for forming minimum area structures for sub-micron CMOS ESD protection in integrated circuit structures without extra implant and mask steps, and articles formed thereby

US Patent 5728612 · Granted Mar 17, 1998

Estimated economic value: $9,863,000 ⓘ

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