Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › OR array architecture for a programmable logic device

OR array architecture for a programmable logic device

US Patent 5701092 · Granted Dec 23, 1997

Estimated economic value: $5,019,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Differential programming of two-terminal resistive switching memory with program2025
Differential programming of two-terminal memory with intrinsic error suppression2025
Differential programming of two-terminal memory with program detection and multi2024
Differential programming of two-terminal resistive switching memory with intrins2024
Differential programming of two-terminal resistive switching memory with program2024
Configuration bit using RRAM2024
Distinct chip identifier sequence utilizing unclonable characteristics of resist2024
Resistive random access memory erase techniques and apparatus2023
Distinct chip identifier sequence utilizing unclonable characteristics of resist2022
Distinct chip identifier sequence utilizing unclonable characteristics of resist2022
Distinct chip identifier sequence utilizing unclonable characteristics of resist2022
Distinct chip identifier sequence utilizing unclonable characteristics of resist2022