Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Optimal pad location method for microelectronic circuit cell placement

Optimal pad location method for microelectronic circuit cell placement

US Patent 5638293 · Granted Jun 10, 1997

Estimated economic value: $8,723,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods for rapid detection of immunogenic epitopes in biothreat agents and emer2024
Dynamically-adaptive live therapeutic agents and methods of use thereof2023
Dynamically-adaptive live therapeutic agents and methods of use thereof2020
Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS proce2015
Via-configurable high-performance logic block involving transistor chains2015
Data shredding RAID mode2014
Via-configurable high-performance logic block architecture2014
Method and apparatus for generating memory models and timing database2013
Method and computer program for generating grounded shielding wires for signal w2013
Method and apparatus for generating memory models and timing database2012
Method and apparatus for balancing signal delay skew2012
Memory mapping for parallel turbo decoding2012